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R2A20111SP/DD
Power Factor Correction Controller IC
REJ03F0231-0100 Rev.1.00 Mar 28, 2007
Description
The R2A20111 is a power-factor correction (PFC) controller IC. This IC adopts continuous conduction mode as PFC operation. Various functions such as constant power limit, overvoltage detection, overcurrent detection, soft start, feedback-loop disconnection detection, and holding function of PFC operation through momentary outage (PFC hold function) are incorporated in a single chip. These functions reduce external circuitry. The constant power limit function allows to eliminate a significant amount of coil noise which is generated due to overcurrent detection operation in case of conventional overload. The PFC hold function enables quick recovery by continuing PFC operation after momentary outage. The hold time can be adjusted by an external capacitance. Overcurrent detection pin is separately provided. Latch mode shutdown function is incorporated. A soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting of the output voltage.
Features
* Maximum ratings Power-supply voltage Vcc: 24 V Operating junction temperature Tjopr: - 40 to 125C * Electrical characteristics VREF output voltage VREF: 5.0 V 3% UVLO operation start voltage VH: 10.5 0.9 V UVLO operation stop voltage VL: 9.0 0.7 V PFC output maximum ON duty Dmax-out: 95% (typ.) * Functions Constant power limit function Continuous conduction mode Hold function of PFC operation on momentary outage (PFC hold function) Overvoltage detection Overcurrent detection Soft start Feedback loop disconnection detection IC shutdown function Package lineup: SOP-16 and DILP-16
Applications
* * * * Flat panel display Projector Desktop PC White goods
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 1 of 40
R2A20111SP/DD
Ordering Information
Part No. R2A20111SPW0 R2A20111DDU0 Package Name FP-16DAV DP-16FV Package Code PRSP0016DH-B PRDP0016AE-B Taping Spec. 2000 pcs./one taping product --
System Diagram
Rec+
150 H
B+
680k To FB 680k B+ OUT (385V dc)
T1
Q1 Rec-
From OUT 470F x2 (450V)
from auxiliary
24V 4.7
VRB1
GND
VCC
16
62k
RT 9
VREF
5V Internal Bias
3.6V 0.65V
H
10.5V
27.5V
L 9.0V
UVLO
5V VREF Generator
6
VREF In GOOD Out
VREF
0.1
CT 10
390p
Reset: Vcc<4V Shut down
R S
Q Q
UVL
R
Q Q
Gate Driver +/- 1.0A (PEAK)
VREF CAO 6800p 2.2k
S
7
470p 82k
Imo = K x {IAC x (VEO - 1V)}
To Q1 gate
R S
Q Q
1
OUT
DELAY RESET
VREF
SS
IAC
CAMP
12
1.28M
1000p
IAC
VE O
IMO
VREF
K
CAI
2.4k VREF 22k 100
RT
5
PFC DELAY
3
1.2V
DELAY
0.22
CLIMIT
10k 0.0165 (5W) 2.4k 100p
CLIMIT
Shut down
8
1.3V
4.0V
CGND EO
4
Gain
RT
820k
14
2.5V
VREF
VREF
0.033
VAMP FB 13
2.688V 2.638V
15
B+OVP 25A
0.47
SS
From VRB1(B+ monitor1)
S Q
FB LOW
0.52V 720k
R Q
2
PFC-OFF
GND
PFC-ON
1
11
0.1
Circuit Ground
14k
0.82V 0.79V
VREF GOOD
IN OUT PFC DELAY
S R
Q Q
DELAY RESET
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 2 of 40
R2A20111SP/DD
Pin Arrangement
OUT 1 GND 2 DELAY 3 CGND 4 CAI 5 VREF 6 CAO 7 CLIMIT 8 (Top view) 16 VCC 15 SS 14 EO 13 FB 12 IAC 11 PFC-ON 10 CT 9 RT
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name OUT GND DELAY CGND CAI VREF CAO CLIMIT RT CT PFC-ON IAC FB EO SS VCC I/O Output -- Input/Output Input Input/Output Output Output Input Input/Output Output Input Input Input Output Output Input Function Power MOS FET gate driver output Ground Hold time adjust and IC shutdown Non-inverting input of current amplifier Inverting input of current amplifier and Current output for PFC control Reference voltage output Current amplifier output Overcurrent detection Timing resistor for settings of operational frequency, and the maximum CAI pin and DELAY pin current Timing capacitor for operational frequency adjust Detection of input AC voltage level Detection of input AC waveform Voltage amplifier input Voltage amplifier output Timing capacitor for soft-start time adjust Power supply voltage input
Description of Pin Functions
OUT Pin: The power MOS FET gate-drive signal is output from this pin, and takes the form of a rectangular waveform with an amplitude of VCC-GND. GND Pin: The ground terminal. DELAY Pin: This pin has two functions; (1) setting the PFC function hold time for cases of momentary outage and (2) IC shutdown. Current that flows through the DELAY pin is in inverse proportion to the RT pin resistance. Source current is 4.7/RT [A] and sink current is 42.3/RT [A]. Normal operation is in the state that sink current flows.
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 3 of 40
R2A20111SP/DD (1) Setting the PFC function hold time for momentary outage When the PFC-ON pin is driven below 0.79 V (typ.) due to a momentary outage, the delay pin functions as source current. PFC operation continues until the capacitor is charged to 1.2 V (typ.). After the voltage on the delay pin reaches 1.2 V (typ.), the pin functions as sink current, and PFC operation terminates. The PFC function hold time can be set by the value of the external capacitor. (2) Shutdown When this pin is pulled up to 4 V (typ.) or higher, the IC enters the shutdown state. Accordingly, the VREF signal becomes low and the operating current becomes several hundred A. The IC does not resume operation until Vcc falls to 4 V (max.) or below. CGND Pin: This pin is the non-inverting input to the current amplifier. CAI Pin: This pin is the inverting input to the current amplifier and functions as source current for PFC control. AC current is controlled to be proportional to the source current and the power factor is corrected. VREF Pin: Temperature-compensated voltage with an accuracy of 5 V 3% is output from this pin. The pin should supply no more than 5 mA (max.) source current. This pin has no sink capabilities. CAO Pin: This pin is the current amplifier output, and is connected to the phase-compensation circuit of the current amplifier. The result of comparison of the voltage on this pin and the CT pin produces the pulse output from the OUT pin. The pulse is limited when the voltage on the CAO pin rises. CLIMIT Pin: This pin is for detecting overcurrent. When the voltage on this pin drops to 1.3 V (typ.) or below, OUT pin is stopped. RT Pin: This pin is for frequency adjustment of the oscillator and connected to GND via resistor. The IC operating frequency is determined by this resistance value and the CT pin capacitance value. Additionally, this resistance value determines the maximum current on the CAI pin and the current on the DELAY pin. CT Pin: This pin is for frequency adjustment of the oscillator and connected to GND via capacitor. The IC operating frequency is determined by this capacitance value and the resistance value of the RT pin. PFC-ON Pin: This pin is applied smoothing voltage of rectified AC voltage and detects the input AC voltage level. When 0.82 V (typ.) or more is applied to this pin, PFC operation starts. When the voltage is 0.79 V (typ.) or lower, the PFC operation stops after the PFC operation hold time (refer to the description of DELAY pin operation). IAC Pin: This pin is for detecting waveform of the input AC voltage. FB Pin: This pin is the input to the voltage amplifier. This pin is applied to voltage divided PFC output with resistors. The feedback loop is intended to keep 2.5 V (typ.). When output voltage rises up and the voltage of this pin is higher than 2.688 V (typ.) or more, the OUT pin is stopped. Moreover, when this voltage of this pin is 0.52 V (typ.) or lower, the OUT pin is also stopped. These functions detect overvoltage, low voltage, and feedback-loop disconnection.
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 4 of 40
R2A20111SP/DD EO Pin: This pin is the output of the voltage amplifier. This pin is connected to the phase-compensation circuit of the voltage amplifier. SS Pin: This pin is connected to GND or VREF via a capacitor. This pin is pulled up to the voltage on the VREF pin until PFC operation starts. When the voltage on the PFC-ON pin has reached 0.82 V (typ.), PFC operation starts and this pin flows 25 A source current. Operation of the CAO pin is affected by that of the SS pin, the pulse width of the OUT pin is limited, and this prevents overshooting when start up. VCC Pin: This pin is for the IC power supply. The IC starts up at 10.5 V (typ.), and stops at 9 V (typ.).
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 5 of 40
R2A20111SP/DD
Absolute Maximum Ratings
(Ta = 25C)
Item Supply voltage OUT peak current OUT DC current Terminal voltage CAO voltage EO voltage DELAY voltage CAI voltage RT current IAC current VREF current Power dissipation Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. Symbol VCC Ipk-out Idc-out Vi-group1 Vi-group2 Vcao Veo Vdelay Vi-cs Irt Iiac Io-ref Pt Tj-opr Tstg Ratings 24 1.0 0.1 -0.3 to Vcc -0.3 to Vref -0.3 to Vcaoh -0.3 to Veoh -0.3 to +6.5 -1.5 to +0.3 -200 0.6 -5 1 -40 to +125 -55 to +150 Unit V A A V V V V V V A mA mA W C C Note 3 4 5
6
Rated voltages are with reference to the GND pin. For rated currents, inflow to the IC is indicated by (+), and outflow by (-). The transient current when driving capacitive load. This is the rated voltage for the following pin: OUT. 5. This is the rated voltage for the following pins: CGND, VREF, CLIMIT, RT, CT, PFC-ON, IAC, FB, SS 6. Thermal resistance of packages Package ja jc Note DIP16 SOP16 120C/W 120C/W -- 50C/W -- 35C/W -- 40 x 40 x 1.6 [mm], Mounted on a glass epoxy printed board with 10% wiring density Infinite heat sink
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 6 of 40
R2A20111SP/DD
Electrical Characteristics
(Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
Supply Item Start threshold Shutdown threshold UVLO hysteresis Startup current Is temperature stability Operating current VREF Output voltage Line regulation Load regulation Temperature stability Initial accuracy fout temperature stability fout voltage stability CT peak voltage Ramp valley voltage RT voltage Soft start Current limit VAMP Sink current Threshold voltage Delay to output Feedback voltage Input bias current Open loop gain High voltage Low voltage Source current Sink current Transconductance 1. Design spec. Symbol VH VL dVUVL Is dIs/dTa Icc Vref Vref-line Vref-load dVref fout dfout/dTa fout-line Vct-H Vct-L Vrt Iss VCL td-CL Vfb Ifb Av-v Veoh Veol Isrc-eo Isnk-eo Gm-v Min 9.6 8.3 1.0 140 -- 3.45 4.85 -- -- -- 58.5 -- -1.5 -- -- 1.17 15.0 1.222 -- 2.40 -0.3 -- 5.2 -- -180 90 150 Typ 10.5 9.0 1.5 200 -0.3 4.5 5.00 5 5 80 65 0.1 0.5 3.6 0.65 1.25 25.0 1.3 100 2.50 0 53 5.7 0.1 -120 120 200 Max 11.4 9.7 2.0 260 -- 6.45 5.15 20 20 -- 71.5 -- 1.5 4.0 -- 1.33 35.0 1.378 200 2.60 0.3 -- 6.2 0.3 -90 180 290 Unit V V V A %/C mA V mV mV ppm/C kHz %/C % V V V A V ns V A dB V V A A A/V Test Conditions
VCC = 9.5 V *
1
IAC = 0 A, CL = 0 F Isource = 1 mA Isource = 1 mA, VCC = 12 V to 23 V Isource = 1 mA to 5 mA Ta = -40 to 125C * Measured pin: OUT Ta = -40 to 125C * VCC = 12 V to 18 V *1 *1 SS = 2 V CLIMIT = 2 to 0 V FB-EO Short Measured pin: FB *1 FB = 2.3 V, EO: Open FB = 2.7 V, EO: Open FB = 1.0 V, EO = 2.5 V FB = 4.0 V, EO = 2.5 V FB = 2.5 V, EO = 2.5 V
1 1
Oscillator
Note:
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 7 of 40
R2A20111SP/DD
Electrical Characteristics (cont.)
(Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
CAMP Item Input offset voltage Open loop gain High voltage Low voltage Source current Sink current Transconductance IAC pin voltage Imo current 1 Imo current 2 Imo current 3 Imo current 4 OUT Minimum duty cycle Maximum duty cycle Rise time Fall time Low voltage Symbol Vio-ca Av-ca Vcaoh Vcaol Isrc-ca Isnk-ca Gm-c Viac Imo1 Imo2 Imo3 Imo4 Dmin-out Dmax-out tr-out tf-out Vol1-out Vol2-out Vol3-out Voh1-out Voh2-out Vshut Vres Ishut Min -- -- 5.2 -- -135 67 530 1.6 -61.3 -197.9 -32.8 -110.4 -- 90 -- -- -- -- -- 11.5 10.0 3.30 -- 120 Typ (-10) 68 5.7 0.1 -90 90 700 2.3 -51.5 -165 -27 -92 -- 95 30 30 0.05 0.5 0.03 11.9 11.0 4.00 -- 190 Max 0 -- 6.2 0.3 -67 135 1000 3.0 -41 -131.5 -21.2 -73.6 0 98 100 100 0.2 2.0 0.7 -- -- 4.70 4.0 260 Unit mV dB V V A A A/V V A A A A % % ns ns V V V V V V V A Test Conditions * *1
1
IAC/ Multiplier
CAO = 2.5 V CAO = 2.5 V *1 IAC = 100 A EO = 2.5 V, IAC = 150 A PFC-ON = 1.2 V EO = Vcaoh, IAC = 150 A PFC-ON = 1.2 V EO = 2.5 V, IAC = 375 A PFC-ON = 2.5 V EO = Vcaoh, IAC = 375 A PFC-ON = 2.5 V CAO = 4.0 V CAO = 0 V CL = 1000 pF CL = 1000 pF Iout = 20 mA Iout = 200 mA (Pulse test) Iout = 10 mA, VCC = 5 V Iout = -20 mA Iout = -200 mA (Pulse test) Input: DELAY Input: Vcc VCC = 9 V
High voltage Shut down Shut down voltage Reset voltage Shut down current
Note:
1. Design spec.
CAO
VE O
IAC
IAC
K
CAMP
Oscillator
Imo
Imo = K x {IAC x (VEO - 1V)}
CAI
1.3V
CGND CLIMIT
CLIMIT
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 8 of 40
R2A20111SP/DD
Electrical Characteristics (cont.)
(Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
Supervisor Item PFC enable voltage PFC disable voltage PFC disable delay threshold voltage Input current B+ OVP set voltage B+ OVP reset voltage FB low set voltage DELAY source current DELAY sink current Note: Symbol Von-pfc Voff-pfc Vd-pfc Ipfc-on dVovps dVovpr Vfbls Isrc-delay Isnk-delay Min 0.74 0.71 1.05 -1.0 0.125 0.075 0.425 -47.5 -- Typ 0.82 0.79 1.20 -0.2 0.188 0.138 0.52 -42.5 770 Max 0.9 0.86 1.30 1 0.250 0.200 0.615 -38 -- Unit V V V A V V V A A Test Conditions Input pin: PFC-ON Input pin: PFC-ON Input pin: DELAY PFC-ON = 2 V Input pin: FB *1 Input pin: FB * Input pin: FB DELAY = 1 V RT = 27 k DELAY = 1 V 2 RT = 27 k *
1
1. dVovps = Vovps - Vref x 0.5 dVovpr = Vovpr - Vref x 0.5
FB
Vovps Vfbls
Vovpr
Vref x 0.5
OUT
2. Design spec.
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 9 of 40
R2A20111SP/DD
Timing Chart
1. Startup and Stop Timing
VCC
10.5V (VH) 5V 4.0V
9.0V (VL)
VREF
VREF GOOD (Internal signal)
PFC-ON
0.82V (Von-pfc)
PFC-OFF (Internal signal)
SS CAO Soft start
CAO SS
CAO CT OUT
FB
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 10 of 40
R2A20111SP/DD 2. Stop Timing by PFC-ON Pin
0.79V (Voff-pfc) PFC-ON
1.2V(Vd-pfc) DELAY
PFC-OFF (Internal signal)
PFC hold time
td-pfcoff
SS
OUT
Normal control
FB
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 11 of 40
R2A20111SP/DD 3. Oscillator, Gate Drive Output
CT
CAO
Dead Time (Internal signal)
OUT (Leading edge control)
4. PFC Operation On/Off
0.82V(Von-pfc) 0.79V(Von-pfc)
PFC-ON
PFC-OFF (Internal signal)
1.2V(Vd-pfc)
DELAY
OUT
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 12 of 40
R2A20111SP/DD 5. FB Supervisor
Vovps
FB
Vovpr 0.52V(FB LOW)
B+OVP (Internal signal)
FB LOW (Internal signal)
SS
OUT
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 13 of 40
R2A20111SP/DD
Description of Functions
1. UVL Circuit The UVL circuit monitors the Vcc voltage. When the voltage is lower than 9.0 V, the IC is stopped. When the voltage is higher than 10.5 V, the IC is started. When operation of the IC is stopped by the UVL circuit, the driver circuit output is fixed low, and output of VREF and the oscillator are stopped.
VCC
10.5V (VH)
9V (VL)
5V VREF 4.0V CAO
CT
OUT
Figure 1 UVL Operation
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 14 of 40
R2A20111SP/DD 2. Operating Frequency The R2A20111 operating frequency fosc is determined by adjusting the timing resistor Rt (the RT pin, pin 9) and the timing capacitance Ct (the CT pin, pin 10). The operating frequency is approximated by the following expression:
fosc = 1.755 x 106 (kHz) Rt (k) x Ct (pF)
Make sure to use a 7 k or more resistance because of the maximum rating of the RT-pin. Meanwhile, as the resistance increases, the IC will become more susceptible to noise, etc. The resistance, therefore, should be up to about 100 k. Also, use a 100 pF or more for the timing capacitance to reduce effects from parasitic capacitance and noise. When the IC is operated at high frequencies, the expression becomes less accurate due to the IC internal delay time, etc. Please confirm operation the value with the actually mounted IC. The maximum operating frequency is 400 kHz. As a reference, the operating frequency data when the timing resistor and the timing capacitance are changed is shown in the figure below.
1000
Operating Frequency (kHz)
100
Timing capacitance Ct 470pF 1000pF 2200pF
10
4700pF
1 1 10 Timing Resistance (k) 100
Figure 2 Operating Frequency Characteristics
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 15 of 40
R2A20111SP/DD 3. Soft Start This function gradually increases the pulse width of the OUT pin from a 0% duty cycle at the startup. By preventing a sudden increase of the pulse width, potential problems such as transient stress on the external parts, overshoot of the PFC output voltage (B+ voltage), or coil noise generated due to overcurrent will be prevented. Although the duty cycle is controlled by the CAO signal, operation of the CAO pin is affected by the voltage on the SS pin during the soft start. When the voltage on the CAO pin reaches the required voltage level, the soft start ends and operation transfers to the normal control. The soft-start time can be set by an external capacity.
0.82V CAO SS SS
PFC-ON
CAO
CT
OUT
PFC output voltage
CT
10
GATE DRIVER +/-1.0A(PEAK)
CAO
7
To Power MOS FET gate
VREF
-+
VREF
1
OUT
CAI
Full-wave rectified AC
5
CAMP
- +
VREF VREF 0.47
CGND
720k
4
PFC-ON
1 14k
15 11
SS
25A
Figure 3 Soft-Start Operation Waveform
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 16 of 40
-+
0.82V 0.79V
R2A20111SP/DD 4. PFC-ON Pin Function The PFC-ON pin is applied smoothing voltage of rectified AC voltage. Accordingly, the AC voltage state is detected and each function depending on the power-supply state is operated. Details of their operation are given below. Note, however, that the functions do not operate when VREF voltage is lower than 4 V as UVL operation and shutdown state.
Full-wave rectified AC 720k
Multiplier Gain selector
VREF
-0.2
PFC-ON
1 14k
5 0.82V 0.79V
Gate Driver +/- 1.0A(PEAK)
PFC-ON/OFF control
VREF
To Power MOS FET gate
1
OUT
VREF
0.47
SS
15 25A
VREF
4.7 RT
[A]
1.2V
DELAY
0.22
3
Constant current circuit
RT
9
RT
42.3 [A] RT
Figure 4 Internal Circuits Connected to the PFC-ON Pin
4-1. Power-Supply Startup Operation When the AC voltage is applied, the voltage on the PFC-ON pin rises and the PFC output voltage is charged to about 2 x AC voltage. After the voltage on the PFC-ON pin exceeds 0.82 V, the voltage of the SS pin starts to be discharged and PFC operation starts. Once the PFC operation starts, the PFC output voltage is boosted to the prescribed voltage.
Full-wave rectified AC
0.82V PFC-ON
SS CAO CAO SS
PFC output voltage
Figure 5 Waveform in Operations in Startup
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 17 of 40
R2A20111SP/DD 4-2. Multiplier Gain Switching Multiplier gain is switched according to the input AC voltage. 4-3. Operation on a Momentary Outage (PFC operation hold on momentary outage: PFC hold function) (1) When the Momentary Outage is Short During a momentary outage, the voltage on the PFC-ON pin is discharged. When it reaches 0.79 V, charging of the capacitor on the DELAY pin starts. When AC-voltage input is resumed, and the voltage on the DELAY pin doesn't reach 1.2 V before the voltage on the PFC-ON pin rises above 0.82 V, The PFC output voltage resumes quickly since the soft-start function is not operated. When the voltage on the PFC-ON pin falls below 0.6 V during a momentary outage, the source current of the PFCON pin starts to increase. As the voltage on the PFC-ON pin becomes low, the amount of current increases. Since the external resistor is connected to GND, the voltage on the PFC-ON pin is balanced between the source current and the voltage determined by the resistance. This function prevents increase of AC current right after AC-voltage input is resumed.
Full-wave rectified AC
PFC-ON
0.79V
0.82V
Ipfc-on
1.2V
DELAY
OUT
PFC output voltage
Figure 6 PFC Hold Function Operation Waveform 1 The hold time for PFC operation is adjusted by the value of the capacitance on the DELAY pin. Note, however, that if VCC voltage of the IC is not normally supplied during a momentary outage, the PFC-ON hold function does not operate.
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 18 of 40
R2A20111SP/DD (2) When the Momentary Outage is Long When the momentary outage is long enough that the DELAY pin voltage reaches 1.2 V, OUT is stopped and SS is reset, then PFC operation is stopped. The current on the PFC-ON pin switches from source current to sink current and the voltage on the PFC-ON pin falls. When the supply of AC voltage resumes, the IC is restarted in a soft-start operation.
Full-wave rectified AC
PFC-ON
0.79V
0.82V
Ipfc-on 1.2V DELAY
SS
OUT
Soft start
PFC output voltage
Figure 7 PFC Hold Function Operation Waveform 2 Note: When the PFC output voltage is driving a heavy load, the PFC output voltage falls rapidly, and the FB pin may fall below 0.52 V before the DELAY pin reaches 1.2 V. Here, the OUT pin is stopped, and the SS pin is reset by the FB pin low-voltage detection circuit.
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 19 of 40
R2A20111SP/DD 5. FB Pin Function The FB pin is a feedback input for the PFC output voltage. This pin is applied to voltage divided PFC output with resistors. The PFC output voltage is controlled so that the voltage on FB becomes 2.5 V. The FB pin function provides protection against abnormal PFC output voltages. The protective functions include overvoltage detection and lowvoltage detection. These functions do not operate when VREF voltage is lower than 4 V as UVL operation and shutdown state.
EO
820k
14 Gate Driver +/- 1.0A(PEAK)
0.033
To Power MOS FET gate
1 PFC output voltage
OUT
680k FB 2.5V
5
V-Amp
2.688V 2.638V
FB Control
B+OVP
0.50V
FB-Low
0.52V
VREF
0.47
VREF
SS
15 25A
Figure 8 Internal Circuits Connected to the FB Pin
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 20 of 40
R2A20111SP/DD 5-1. Power-Supply Startup Operation When the AC voltage is applied, the PFC-ON pin voltage starts to rise up. After it has reached 0.82 V, the voltage on the SS pin starts to be discharged and PFC operation is started with the soft-start function. Once the PFC operation is started, the voltage on the FB pin rises and is controlled so that it reaches 2.5 V.
Full-wave rectified AC
0.82V PFC-ON SS CAO CAO SS 2.5V FB
PFC output voltage
Figure 9 Waveform in Startup Operation
5-2. Operation when the Power-Supply Stops When the supply of AC voltage stops, both of the PFC output voltage and the voltage on the FB pin fall. When the voltage on the FB pin is lower than 0.52 V, the PFC operation stops and the SS pin is reset.
Full-wave rectified AC
FB
0.52V
OUT
SS
Figure 10 Waveform in Stop Operation Note: When the PFC output voltage is driving light load, the PFC output voltage falls slowly, and the PFC-hold function may be activated before the voltage on the FB pin falls to 0.52 V. In this case, the PFC hold function operates, stopping output on the OUT pin and resetting the SS pin.
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R2A20111SP/DD 5-3. Overvoltage Operation When the PFC output voltage is larger than 7.5% of the prescribed voltage due to an abnormality in the system or a sudden change of AC voltage or load, operation of the OUT pin is stopped. When the PFC output voltage returns to within 5.5% of the prescribed voltage, operation of the OUT pin is resumed.
107.5% of the output voltage
PFC output voltage
105.5% of the output voltage
2.688V
FB
2.668V
OUT
Figure 11 Waveform of Operation after Overvoltage detection by the FB Pin
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 22 of 40
R2A20111SP/DD 6. IC Shutdown Function When the DELAY pin is pulled up to 4 V, the IC shutdown function operates. During shutdown, the IC enters the standby state. To reset the circuit from the shutdown state, the voltage on VCC must be lowered to 4 V or less. After this reset, when the VCC pin voltage reaches 10.5 V, the IC is restarted.
VCC
9V 4.0V
10.5V
4V DELAY
Internal latch
Latched state
VREF
Figure 12 Waveform of Operation in IC Shutdown
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 23 of 40
R2A20111SP/DD
Main Characteristics
Standby Current vs. Power Supply Voltage Characteristics 250 Ta = 25C 200
Is (A)
150
100
50
0 0 1 2 3 4 5 6 Vcc (V) 7 8 9 10 11
Power Dissipation vs. Power Supply Voltage Characteristics 8 7.5 7 6.5
Icc (mA)
Ta = 25C CL = 1000pF
6 5.5 5 4.5 4 3.5 10 12 14 16 Vcc (V) 18 20 22 24
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 24 of 40
R2A20111SP/DD
Reference Voltage Temperature Characteristics 5.2 5.15 5.1 Vcc = 12V Iref = -1mA
VREF (V)
5.05 5 4.95 4.9 4.85 4.8 -40
-20
0
20
40 Ta (C)
60
80
100
120
Operating Frequency Temperature Characteristics 75 73 71 Vcc = 12V RT= 27k CT = 1000pF
Frequency (kHz)
69 67 65 63 61 59 57 55 -40 -20 0 20 40 Ta (C) 60 80 100 120
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 25 of 40
R2A20111SP/DD
Start-up Voltage Temperature Characteristics 11.5 11.3 11.1 10.9
VH (V)
10.7 10.5 10.3 10.1 9.9 9.7 9.5 -40 -20 0 20 40 Ta (C) 60 80 100 120
Shutdown Voltage Temperature Characteristics 9.6
9.4
9.2
VL (V)
9
8.8
8.6
8.4 -40
-20
0
20
40 Ta (C)
60
80
100
120
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 26 of 40
R2A20111SP/DD
Standby Current Temperature Characteristics 280 Vcc = 9.5V 260 240 220
Is (A)
200 180 160 140 120 -40
-20
0
20
40 Ta (C)
60
80
100
120
Operating Current Temperature Characteristics 7 6.5 6 5.5 5 4.5 4 3.5 3 -40 Vcc = 12V CL = 0pF
Icc (mA)
-20
0
20
40 Ta (C)
60
80
100
120
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 27 of 40
R2A20111SP/DD
CAI Pin Current vs. IAC Pin Current Characteristics 250 Ta = 25C Vcc = 12V Veo = Veoh 200 RT = 27k PFC-ON = 0.5V
CAI Pin Current (A)
150
PFC-ON = 1V PFC-ON = 2V
100 PFC-ON = 3V 50 PFC-ON = 4V PFC-ON = 5V 0 0 100 200 300 IAC Pin Current (A) 400 500 600
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 28 of 40
R2A20111SP/DD
Precautions on Usage
Figure 13 shows symbols which are used in this chapter.
L
Vout
Rcs Isum Rmo CGND
Vout
Rmo
CAI Imo
Ceo1 Rfb1 Rfb2 AC_Rectifier Cpfc
Reo1
Reo2 Rpfc1 Ceo2 Ct Css Rac Rt Rpfc2
10 12V
16
VCC
15
SS
14
EO
13
FB
12
IAC
11
PFC-ON
10
CT CAO
9
RT CLIMIT
R2A20111
DELAY CGND VREF GND OUT CAI
1
2
1000p
3
Cdelay
4
5
6
7
8
Ccao2 Ccao1 Rcao1 Rcao2 Cclimit1
Rref-cai
Rmo
Rmo
Rclimit1 0.1
Rclimit3
Rcs
Rclimit2
Figure 13 Template Illustrating Symbols of External Circuit Elements
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 29 of 40
R2A20111SP/DD 1. Power Limit Function 1-1. Limited Power Value When the load exceeds the rated load, the power is limited by the set power value and the IC enters the constant power control state. This indicates that the power is limited by nearly-constant power independent of the input AC voltage, compared to the conventional overcurrent detection circuit. The limited power value is determined by the values of external resistors and is expressed by the following equation:
Plimit = 1.74 * Rmo * (Rpfc1 + Rpfc2)2 Rcs * Rac * Rpfc22
This is the equation for reference only. Be sure to sufficiently confirm the operation by using the actual circuit board. The actual value may differ from the equation by conditions, but the trend indicated by the equation remains the same (For instance, as the amount of Rmo becomes large, the limited power value increases). Therefore, use the equation above for reference to fine-tune the resistance values. 1-2. Trend of Limited Power Value for Input AC Voltage Although the limited power value is nearly constant with respect to the input AC voltage, it may be deviated to a certain degree from linearity by conditions. When it has a negative slant with respect to the input AC voltage, add a resistor between the CAI pin and the VREF pin so that the deviation from linearity can be corrected to some degree. 1-3. Limit on Constant Power Function After the PFC power supply enters the constant power operation state and load increases further, the PFC output voltage reaches about 2 x input AC voltage. At this point the PFC output voltage is unable to fall below the point in principle of the boost converter. If the load increases further at this point, current increases on the peak part of input current, then the power starts increasing again. This current cannot be controlled by the IC.
PFC Output Voltage
PFC Output Power
Constant power curve 2Vac
Rise in power for the reason that the AC voltage is high and the output voltage is unable to fall below 2 Vac.
PFC Output Current
PFC Output Current
Figure 14 Outline of Constant Power Limit Function
1-4. Effects on Power Limit Characteristics of Resistor Rcao1 of CAO Pin As the external resistance Rcao1 of the CAO pin is small, the limited power value decreases. This decrease is caused by rise of the voltage on the EO pin in principle as Rcao1 becomes small. When the load becomes heavy and the voltage on the EO pin is clamped at the upper limit, the IC is operated in the power limit operation mode. Therefore, since the voltage on EO pin increases, the power limit value decreases relatively.
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 30 of 40
R2A20111SP/DD 1-5. Relations between RT Resistor and Power Limit The maximum current on the CAI pin is expressed in inverse proportion to the resistance of the RT pin as 4.7/RT. Since Imo is proportional to the input AC current, when the value of AC voltage drops, Imo rises. Imo is, however, limited by the above maximum current value. If the value of Imo (max.) is set higher than the required current value with the minimum input AC voltage, the power limit function is operated in all range of input AC voltage without any difficulty. If the value of Imo (max.) is smaller than the required current, the rated power can not load (see figure 15).
Imo
RT increases
Limit power
Power
Rated power Area where the rated power cannot load RT increases
Range of input AC voltage
Figure 15 RT and Power Limit In case of sudden turn from low AC voltage to high AC voltage as in return from a momentary outage or sag, the voltage on the PFC-ON pin changes after the AC voltage for its smoothing capacitance. Therefore, the voltage on the PFC-ON pin remains low while the AC voltage is high. In such a state, the current is controlled to increase transiently (see figure 16). The overcurrent detection circuit is operated due to this increase in current, and noise of an inductor may be generated. In this case, set the limitation on current by adjusting the RT pin resistance to prevent the operation of overcurrent detection circuit.
Full-wave rectified AC
PFC-ON pin
AC current
Figure 16 Increase in Current due to AC Voltage Sag
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 31 of 40
R2A20111SP/DD 1-6. Tolerance of Limited Power Values The tolerance of the limited power values depend on the tolerance of the CAI pin current. Since overcurrent detection value is constant, set the RT resistance as illustrated in figure 17, so that the resistance does not exceed the overcurrent detection level. Seen in figure 17, the key to select a switching device is not the tolerance in the limited power value but in the current value limited by RT. The tolerance of this current ranges from - 10% to + 10%.
Limited power value in case of only the overcurrent protection
Power
Limited power
Rated power
Isum (peak)
Overcurrent detection level
Input AC voltage
Current limited by RT
Figure 17 Overcurrent Detection Level and Power Limitation
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 32 of 40
R2A20111SP/DD 2. Operation of PFC On/Off Function PFC function of the R2A20111 can be turned on and off externally using the following methods. (1) Pull down the voltage on the PFC-ON pin to the GND level. (2) Pull up the voltage on the SS pin to the VREF voltage level. (3) Pull down the voltage on the CLIMIT pin to 1.3 V or lower. (4) Pull up the voltage on the DELAY pin to 4 V or more. Since the voltage on the OUT pin is fixed to the GND level in each case, the boost operation is halted. The sections from 2-1 to 2-4 describe phenomena which may occur for functional reasons of the IC. Make sure to sufficiently confirm each operation using the actual the power-supply board. When the current flows transiently and noise of an inductor is generated, refer to section 1-5 "Relations between RT Resistor and Power Limit". 2-1. On/Off Operation by Using the PFC-ON Pin When the voltage on the PFC-ON pin drops, the IC controls to increase the AC current. Therefore, the AC current is controlled to increase while the voltage on the PFC-ON pin is pulled down. Furthermore, the PFC-ON pin has the PFC hold function. Since the PFC operation is not halted during the hold periods, the control current increases during this period (see figure 18). Also, when the PFC function is turned off in the light load, the output voltage may rise due to this increase current.
Full-wave rectified AC
PFC-ON pin
0.79V 1.2V
0.82V 0V
DELAY pin
AC current
PFC hold time
Soft start
Figure 18 On/Off Operation by PFC-ON pin
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 33 of 40
R2A20111SP/DD 2-2. On/Off Operation by Using the SS Pin When the voltage on the SS pin is pulled up to the VREF voltage level, the voltage level of the CAO pin is also pulled up together with the SS pin. Then, the OUT pin is stopped. After the voltage level of the SS pin is pulled up, a few pulses on the OUT pin may be generated by capacitance of the phase-compensation circuit of the CAO pin (see figure 19). The circuit to directly pulls up the CAO pin is not recommended since the circuit may affect the phase-compensation circuit of the current amplifier.
SS pin voltage
CAO pin voltage
OUT pin voltage
Figure 19 On/Off Operation by Pulling up SS Pin 2-3. On/Off Operation by using the CLIMIT Pin When the voltage on the CLIMIT pin falls to 1.3 V or lower, the pulses on the OUT pin stop by the overcurrent detection circuit. When the voltage of the CLIMIT pin is released, the pulses on the OUT pin is resumed without soft start. 2-4. On/Off Operation by Using the DELAY Pin When the voltage on the DELAY pin is pulled up to 4 V or more, the IC enters the shutdown state and the pulses on the OUT pin is stopped. Since the shutdown function is operated in latch mode, the IC is not resumed even when the voltage level of the DELAY pin is pulled down. The IC resumes only when lower the voltage on the VCC pin to 4 V or lower once and raise the voltage on the VCC pin higher than the UVL voltage. Figure 20 illustrates an example of detection circuit.
VREF PFC output voltage
1
DELAY pin
5
2
M51958BL
3 4
GND
Figure 20 Example of Shutdown Circuit
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 34 of 40
R2A20111SP/DD 3. Overcurrent Detection Circuit When the RC filter is added the CLIMIT pin to prevent noise errors (see figure 21), the cut-off frequency shifts on the lower frequency side than the added RC filter because of the Rclimit 1 and Rclimit 2. This causes possibility that exactly current can not detect.
VREF Rclimit1 R CLIMIT Rcs Rclimit2 C
Figure 21 Example of CLIMIT Pin Filter Since the overcurrent is detected by coil current, the detected current value is not the same as the peak value of the AC input current (see figure 22). Because of this difference, the overcurrent detection circuit is operated before the power reaches the constant power limit, and noise of an inductor may occur. In such a case, raise the overcurrent detection level.
I Overcurrent detection level AC input current peak Difference in current is approximated by the following equation: 2 x Vac x D x fosc I = 2xL Vac: input AC voltage L: Step-up coil inductance D: IC OUT pin ON Duty fosc: IC operating frequency
Coil current
Figure 22 AC Input Current and Coil Current
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 35 of 40
R2A20111SP/DD 4. PFC Hold Function The PFC hold time can be adjusted by changing the value of the capacitor connected to the DELAY pin. The capacitance is charged with the source current from the IC and the PFC hold function is operated until the voltage on the DELAY pin reaches 1.2 V. Although the PFC-ON pin detects an occurrence of the momentary outage, the detection delay time occurs because a smoothing capacitor is connected to the PFC-ON pin. This delay time depends on the value of a resistor and the value of a smoothing capacitor which are connected to the PFC-ON pin. Therefore, the hold time is dependent on the following: (a) Value of the capacitor connected to the DELAY pin (b) Current value of the DELAY pin (c) Values of the resistor and the capacitor connected to the PFC-ON pin Actual PFC hold time thold is expressed in the following equation (see figure 23):
thold = t1 + t2 - t3 t1 = -Rpfc2 * Cpfc * In 0.79V VPFC-ON
t2 + t3 = CDELAY *
1.2V Isrc-delay 0.82V - * In 0.4V - 2 * 2 * VAC 2 * 2 * VAC
t3 = -Cpfc *
Rpfc1 * Rpfc2 Rpfc1 + Rpfc2
Isrc-delay =
4.7V RT 2 * 2 * VAC * Rpfc2 Rpfc1 + Rpfc2
VPFC-ON =
Full-wave rectified AC
PFC-ON pin
0.79V
0.82V 0.4V 1.2V
DELAY pin t2 t1 thold t3
Figure 23 PFC Hold Time
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 36 of 40
R2A20111SP/DD 5. Precautions on Pins 5-1. OUT Pin Undershoot may occur on the PWM pulse of the OUT pin because of a parasitic inductance of wiring, etc. This undershoot (negative electric potential) may cause errors of the IC. In such a case, use a Schottky barrier diode, etc. to suppress the undershoot. 5-2. DELAY Pin When the voltage on the DELAY pin reaches 4 V or more, the shutdown function is operated and the IC enters the shutdown state. Since the shutdown state is in latch mode, the IC is not resumed unless the voltage on the VCC pin is, once, lowered to 4 V or below. When the PFC hold function is not used, lower the DELAY pin capacitance as possible. However, connect a capacitor with a few thousands pF or more capacitance to the DELAY pin so that the shutdown function will not be operated due to noise, etc. and note wiring pattern not to catch the noise. 5-3. CAI Pin and CLIMIT Pin These pins are connected to a current detection resistor via a resistor. Provide a rush-current protection circuit, not to exceed the maximum rating because of the rush current at the startup of power supply. 5-4. VREF Pin The voltage on the VREF pin is a reference voltage in the IC. For stabilizing the voltage on the VREF pin, be sure to connect a capacitor between the VREF pin and GND. However, in capacitance of a capacitor to be connected, overshoot may occur at the rising of the VREF pin (see figure 24). Pay special attention to this point when the voltage on the VREF pin is used as the power supply for an external circuit and a reference voltage. Furthermore, note that the source current of the VREF pin will not exceed the maximum rating.
Vref Overshoot
Vref Peak Voltage (V)
7 6.5 6 5.5 5 0.01
0.1 Cref (F)
1
Figure 24 Overshoot Amount on VREF Pin (Reference Data)
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 37 of 40
R2A20111SP/DD 6. Pattern Layout In designing the pattern layout, pay as much attention as is possible to the following points. (1) Place the IC pins (particularly, CGND, CAI, PFC-ON, IAC, FB) and their wiring as far from high-voltage switching lines (particularly the drain voltage for the power MOSFET) as possible and in general design the wiring to minimize switching noise. (2) Wiring between CGND and Rcs via Rmo and wiring between CAI and RCS via Rmo connect nearly and separately to Rcs. (3) It is probable that stability operation is achieved by inputting signals via low pass filter to CLIMIT, PFC-ON, IAC, FB terminal. (4) Place a resistors and capacitors connect VREF , RT, CAO, CT, VCC as close to the IC as possible, and keep the wiring short. (5) Pattern layout priority (for reference) 1. Place the IC as far from high voltage switching lines as possible. 2. The pattern of the GND should be as wide as possible. 3. Place the stabilizing capacitor for VREF as close to the IC as possible. 4. Place the stabilizing capacitor for VCC as close to the IC s possible. 5. Place the resistors and capacitors (Rcao1, Rcao2, Ccao1, Ccao2) for CAO as close to the IC as possible. 6. Wiring between CGND and Rcs via Rmo and Wiring between CAI and Rcs via Rmo connect nearly and separately to Rcs. 7. Place the timing resistor for RT as close to the IC as possible. 8. Place the timing capacitor for CT as close to the IC as possible. 9. Place the resistors and capacitors (Reo1, Reo2, Ceo1, Ceo2) for EO as close to the IC as possible. 10. Place the resistors and capacitors (Rpfc1, Rpfc2, Cpfc) for PFC-ON as close to the IC as possible. 11. Place the resistors (Rfb1, Rfb2) for FB as close to the IC as possible. 12. Place the resistors (Rac) for IAC as close to the IC as possible. 13. Place the resistors (Rclimit1, Rclimit2) for CLIMIT as close to the IC as possible. 14. Place the capacitor (Cdelay) for DELAY as close to the IC as possible. 15. Place the capacitor (Css) for SS as close to the IC as possible.
Vout
Rfb1 Ceo1
Rfb2 AC_Rectifier Cpfc
Reo1
Reo2 Rpfc1 Ceo2 Ct Css Rac Rt Rpfc2
10 12V
16
VCC
15
SS
14
EO
13
FB
12
IAC
11
PFC-ON
10
CT CAO
9
RT CLIMIT
R2A20111
DELAY CGND
1
2
1000p
3
Cdelay
4
5
VREF
GND
OUT
CAI
6
Ccao2 Rcao2
7
Ccao1
8
Rcao1
Rmo
Rmo
0.1
Rclimit1
Rcs
Rclimit2
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 38 of 40
R2A20111SP/DD (6) There is a potential that placing the heat sink between ICs and power MOSFET will be a some kind of shield and reduce the radiation noise (figure 25).
IC
Heat sink
F E T
Heat sink
F E T
IC
Figure 25 Example of Layout of Parts
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 39 of 40
R2A20111SP/DD
Package Dimensions
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
JEITA Package Code P-DIP16-6.3x19.2-2.54
RENESAS Code PRDP0016AE-B
Previous Code DP-16FV
D
16
A
MASS[Typ.] 1.05g
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
REJ03F0231-0100 Rev.1.00 Mar 28, 2007 Page 40 of 40
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